SPL-G1 is not a general-purpose CPU/GPU. It is a dedicated security primitive — a hardware causal-audit Trusted Compute Unit (TCU) that delivers provable, hardware-level causal audit across the entire compute lifecycle. Every operation is anchored to an immutable causal chain.
Where conventional processors separate computation from trust, SPL-G1 fuses them: the audit is part of the silicon, not a layer bolted on after the fact.
A real half-precision floating-point datapath (sign / 5-bit exponent / 10-bit mantissa) with subnormal, NaN and ±Inf handling — not a fixed-point approximation. Verified in RTL simulation.
splcc compilerA C-subset compiler (splcc.py v0.1) that lowers C into SPL-G1 microcode, plus
splcc_bridge.py for host-side integration. High-level intent becomes auditable hardware flow.
A parameterized 256-entry program memory with JMP / JZ / JNZ / CALL / RET / HALT, an 8-deep return stack and out-of-bounds protection. The RA-BUS READ transaction state drives the external data channel (A4).
Each operation is sealed to a 256-bit anchor through an SBC fuse. Once fused, the causal chain is immutable — the root of provable auditability.
Hard-constraint checking via an all-ones constraint_bits comparison plus a 56-bit dependency
mask with cascade invalidation. Pass-through mode always passes; configured rules are enforced at dispatch.
A two-dimensional in-memory-compute array coupled to a 4-target RA-BUS (compute / sequencer / external memory / anchor) — data-centric flow with no stored-program bottleneck between memory and compute.
splcc v0.1 (C → microcode) + splcc_bridge.pyMilestones A1 (control-flow), A2 (FP16), A3 (compiler), A4 (data channel) and A6 (SBC fuse) are delivered and verified in RTL simulation. A5 causal constraints are at the v2 level; the programmable per-class mask is planned.